EDA/Semiconductor

• Advanced Micro Devices (AMD)
  Application: Luther
  AMD deploys the test generator, Luther, internally to find bugs in the company's complex microprocessor designs. AMD produces processors for Microsoft Windows™ compatible PCs, flash memories, communications products, networking applications and programmable logic devices.

• American Microsystems, Inc. (AMI)
  Application: Access Design Tools™
  One of the tools in the Access Design Tool suite is NETRANS, used to convert a customer's Field Programmable Gate Array (FPGA) to an optimized ASIC design. "There are many reasons why a customer might want to make this conversion," says Kirk. "By far the most common is to substantially reduce costs. FPGAs can be really large chips," he explains. "There is a lot of silicon and a lot of pins, but often the same design can be implemented using a minimal amount of silicon with fewer pins. FPGAs can sell for as much as several hundred dollars each while AMI can produce equivalent ASIC chips for as little as ten to fifteen dollars each in volume."

• Cadence Design Systems, Inc.
  Application: Design Planner
  Design Planner comprises three products, Top-Down DP, Logic DP, and Physical DP. All three contribute to the end-result of creating an IC (integrated circuit) floor plan. Top-Down DP begins the initial phase of the floor plan design, allowing the user to start accounting for the physical floor plan even during the early phases of behavioral design using a hardware description language. Logic DP starts with the gate level net list obtained from Top-Down DP and ends at the point where real placement occurs. Physical DP begins with the full placement obtained with Logic DP and ends with the full routing of cells and thereby full routing of the circuit. At this stage, the circuit is completely wired.

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